Pin access hybrid cell height design and system

ABSTRACT

A method of generating a layout diagram for an integrated circuit includes arranging a plurality of cells in the layout diagram, wherein each cell of the plurality of cells comprises a first power rail along a first boundary and a second power rail along a second boundary, and the first boundary is spaced from the second boundary in a first direction. The method further includes placing a plurality of cell pins over a plurality of selected via placement points in a first cell of the plurality of cells in accordance with a design rule, wherein a first cell pin of the plurality of cell pins has a first end spaced from both the first power rail and the second power rail in the first direction.

PRIORITY CLAIM

This application is a divisional of U.S. application Ser. No.17/332,646, filed May 27, 2021, which is a continuation of U.S.application Ser. No. 16/995,509, filed Aug. 17, 2020, now U.S. Pat. No.11,222,157, issued Jan. 11, 2022, which is a continuation of U.S.application Ser. No. 16/556,928, filed Aug. 30, 2019, now U.S. Pat. No.10,769,342, issued Sep. 8, 2020, which claims priority to U.S.Provisional Application No. 62/753,427, filed Oct. 31, 2018, the entirecontents of which are incorporated by reference herein.

BACKGROUND

Scaling of semiconductor devices follows Moore's Law in the past fewdecades. As advances in manufacturing processes are independently unableto keep up with the constant device scaling trend due to lithography andintegration limitations, layout design techniques also help to furtherscaling of semiconductor devices.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the followingdetailed description when read with the accompanying figures. It isnoted that, in accordance with the standard practice in the industry,various features are not drawn to scale. In fact, the dimensions of thevarious features may be arbitrarily increased or reduced for clarity ofdiscussion.

FIG. 1 is a flowchart of a method of generating a layout diagram of anintegrated circuit (IC), in accordance with some embodiments.

FIGS. 2A-2F are depictions of a layout diagram at various stages ofgenerating the IC layout diagram, in accordance with some embodiments.

FIG. 3 is a flowchart of a method of generating a layout diagram of anIC, in accordance with some embodiments.

FIGS. 4A-4C are depictions of a layout diagram at various stages ofgenerating the IC layout diagram, in accordance with some embodiments.

FIG. 5 is a block diagram of an electronic design automation (EDA)system, in accordance with some embodiments.

FIG. 6 is a block diagram of an IC manufacturing system and an ICmanufacturing flow associated therewith, in accordance with someembodiments.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, orexamples, for implementing different features of the provided subjectmatter. Specific examples of components, materials, values, steps,operations, materials, arrangements, or the like, are described below tosimplify the present disclosure. These are, of course, merely examplesand are not intended to be limiting. Other components, values,operations, materials, arrangements, or the like, are contemplated. Forexample, the formation of a first feature over or on a second feature inthe description that follows may include embodiments in which the firstand second features are formed in direct contact, and may also includeembodiments in which additional features may be formed between the firstand second features, such that the first and second features may not bein direct contact. In addition, the present disclosure may repeatreference numerals and/or letters in the various examples. Thisrepetition is for the purpose of simplicity and clarity and does not initself dictate a relationship between the various embodiments and/orconfigurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,”“above,” “upper” and the like, may be used herein for ease ofdescription to describe one element or feature's relationship to anotherelement(s) or feature(s) as illustrated in the figures. The spatiallyrelative terms are intended to encompass different orientations of thedevice in use or operation in addition to the orientation depicted inthe figures. The apparatus may be otherwise oriented (rotated 90 degreesor at other orientations) and the spatially relative descriptors usedherein may likewise be interpreted accordingly.

Some integrated circuit (IC) designs are based on a collection of cellsselected from a library. The layout includes at least one logic blockcustomized for a particular use. A logic block is an arrangement ofcells placed in a routing grid of vertical and horizontal routingtracks. Conductive structures, such as metal lines, are placed onrouting tracks to provide connection between cells. The design of an IClayout is carried out by an automatic placement and routing (APR) toolthat includes a placer and a router, by selecting standard cells from alibrary of standard cells and placing and routing the cells according toa number of design rules. The placer determines the optimum location ofeach standard cell of the integrated circuit, and the router optimizesthe routing of input/output lines and the connection between standardcells so that the IC layout does not become overly congested byinput/output and other routing lines.

The placer and router uses a number of design rules to determine whereto place the cells and how to create the wires to connect all the cells.The design rules for example, include minimum length of lines, minimumspacing between lines, and the like. Failure to satisfy a design rulesometimes results in a process-related problem such as shorting betweenmeal lines due to optical proximity, in some instances.

The height of a cell is determined by the number of horizontal tracksextending between the uppermost and lowermost edges of the cell. Cellswith a smaller cell height are used for realizing high integration andlow power consumption, while cells with a higher cell height are usedfor high speed operation. In some logic blocks, the standard cells havea same cell height for easy cell placement and routing.

With the increasing demands for high speed and low power integratedcircuits which are applicable for portable electronic application, logicblocks are modified to include standard cells of different cell heights.In such hybrid cell design, the standard cells are arranged in rows andin one row, only standard cells with the same height are placed.

The hybrid cell design using standard cells of different cell heights inone logic block helps to achieve both high speed and low power in anintegrated circuit layout design. However, in the hybrid cell design,cell pins such as input and output pins used to transmit signals betweencells suffer substantial reductions in end-to-end spacing and pin accessarea. As a result, additional cut masks are used in performing cellrouting. The use of additional cut masks often results in increasedfabrication cost.

In some embodiments, a layout design methodology for implementing cellpin placement and routing for cells of different cell heights isprovided. The layout design methodology allows placing and routing pinsof high speed cells and low power cells in a same logic block withoutthe need of using additional cut masks in order to comply with theexisting design rules. The layout design methodology of the presentdisclosure thus helps to keep the same process cost when changingtraditional uniform cell height design to hybrid cell height design.

FIG. 1 is a flowchart of a method 100 of generating a layout diagram200F of an integrated circuit (IC), in accordance with some embodiments.In various embodiments, the operations of method 100 are performed inthe order depicted in FIG. 1 or in one or more orders other than theorder depicted in FIG. 1 . In some embodiments, one or more additionaloperations are performed before, between, during, and/or after one ormore operations of method 100. Method 100 is described below inconjunction with FIGS. 2A-2F, which include views of various stages ofgenerating a layout diagram 200F.

Some or all of the operations of method 100 are capable of beingperformed as part of an automated placement and routing (APR) tool. Insome embodiments, some or all of method 100 is executed by a processorof a computer. In some embodiments, some or all of method 100 isexecuted by a processor 502 of an electronic design automation (EDA)system 500, discussed below with respect to FIG. 5 . In someembodiments, some or all of the operations of method 100 are capable ofbeing performed as part of a design procedure performed in a designhouse, e.g., a design house 620 discussed below with respect to FIG. 6 .

Referring to FIG. 1 and FIG. 2A, method 100 includes operation 102 inwhich a plurality of first conductive lines 220-228 for a plurality offirst cells 202 having a first cell height and a plurality of secondconductive lines for 232-236 for a plurality of second cells 204 havinga second cell height CH1 less than the first cell height CH2 are placedalong corresponding horizontal routing tracks of a plurality ofhorizontal routing tracks HT1-HT21; first and second cells 202 and 204are arranged into a plurality of rows. FIG. 2A is a layout diagram 200Aof an IC after placing a plurality of first conductive lines 220-228 anda plurality of second conductive lines for 232-236 along correspondinghorizontal routing tracks of a plurality of horizontal routing tracksHT1-HT21, in accordance with some embodiments.

Referring to FIG. 2A, layout diagram 200A includes a plurality of cellsof different cell heights, e.g. first cells 202 of a first cell heightCH1 and second cells 204 of a second cell height CH2, arranged inseparate rows. For simplicity of illustration, layout diagram 200Aincludes four rows, i.e., first row (Row 1), second row (Row 2), thirdrow (Row 3) and fourth row (Row 4). In some embodiments, layout diagram200A includes a number of rows other than four. Each row in theplurality of rows Row 1-Row 4 extends along the X direction. In someembodiments, the X direction is a horizontal direction of layout diagram200A. In some embodiments, the X direction is a direction other thanhorizontal. Rows in the plurality of rows Row 1-Row 4 are abutted to oneanother in the Y direction that is perpendicular to the X direction. Insome embodiments, the Y direction is a vertical direction of layoutdiagram 200A. In some embodiments, the Y direction is a direction otherthan vertical.

The plurality of rows, e.g., Row 1-Row 4, is laid out relative to arouting grid defined by a plurality of horizontal routing tracksHT1-HT21 and a plurality of vertical routing tracks VT1-VT20. Horizontalrouting tracks HT1-HT21 are arranged in parallel along the X direction.Each horizontal routing track HT1-HT21 represents a potential routingpath for an IC along the X direction. In some embodiments, each ofhorizontal routing tracks HT1-HT21 is spaced by an equal distance froman adjacent horizontal routing track HT1-HT21. Vertical routing tracksVT1-VT20 are arranged in parallel along the Y direction. Each verticalrouting track VT1-VT20 represents a potential routing path for the ICalong the Y direction. In some embodiments, each of vertical routingtracks VT1-VT20 is spaced by an equal distance from an adjacent verticalrouting track VT1-VT20. In some embodiments, two adjacent verticalrouting tracks of the plurality of vertical routing tracks VT1-VT20 areseparated by a nominal minimum distance for forming clear patterns witha single exposure of a single photomask at a given technology node(without using a double patterning technique). Thus, the two verticalsecond routing tracks in the plurality of vertical routing tracksVT1-VT20 are designated having the same color (not shown). In someembodiments, odd-numbered vertical routing tracks VT1, VT3 . . . VT19are spaced apart from each other by a minimum distance for forming clearpatterns with a single exposure of a single photomask at a giventechnology node (without using a double patterning technique), andeven-numbered vertical routing tracks VT2, VT4 . . . VT20 are spacedapart from each other by a minimum distance for forming clear patternswith a single exposure of a single photomask at a given technology node(without using a double patterning technique). Thus, a distance (i.e.,pitch P) between two adjacent vertical routing tracks of the pluralityof second routing tracks VT1-VT20 is smaller than the minimum distancepermitted by the single patterning lithography. In FIG. 2A, each ofvertical routing tracks VT1-VT20 is assigned a first color such as ColorA, or a second color such as Color B. Starting with vertical routingtrack VT1, each vertical routing track VT1-VT20 is designated eitherColor A or Color B, such that no two adjacent vertical routing tracksare the same color. In FIG. 2A, every other vertical routing tracksVT1-VT20 is designated the same color. For example, odd-numberedvertical routing tracks VT1, VT3 . . . VT19 are designated Color A, andeven-numbered second routing tracks VT2, VT4 . . . VT20 are designatedColor B. The color (e.g., Color A, Color B) indicates that features withthe same color are to be formed on a same mask of a multiple mask set,and features with a different color are to be formed on a different maskof the multiple mask set.

Cells 202 and 204 are placed by an APR tool during a placement stage toabut one another. Cells 202 and 204 are arranged such that cells placedin the same row have the same cell height, although widths of the cells202 or 204 in the same row vary, in some embodiments. In someembodiments, first cells 202 and second cells 204 are placed alternatelyin the plurality of rows Row 1-Row 4. In FIG. 2A, first cells 202 havingthe first cell height CH1 are placed in the odd-number rows, e.g., Row 1and Row 3, and second cells 204 having the second cell height CH2 areplaced in the even-number rows, e.g., Row 2 and Row 4. In someembodiments, the first cell height CH1 is set to be greater than thesecond cell height CH2. The cell height CH of a cell, e.g., cell 202 or204 is determined by the number of horizontal routing tracks HT1-HT21encompassed between the uppermost edge and lowermost edge of the cell202 or 204. In some embodiments, each first cell 202 has a track heightof seven (7) and each second cell 204 has a track height of five (5).First cells 202 with a relatively large cell height CH1 operate at ahigher speed, and are thus applicable for high speed applications.Second cells 204 with a relatively small cell height CH2 operate withless power, and are thus usable for low power applications. Althoughcells in adjacent rows in FIG. 2A have different cell heights, cells inadjacent rows having the same height are contemplated in the presentdisclosure. In some embodiments and in FIG. 2A, the number of rows inthe plurality of rows for placing first cells 202 is equal to the numberof rows (e.g., Row 1 and Row 3) in the plurality of rows for placingsecond cells 204 (e.g., Row 2 and Row 4). One of ordinary skill in theart would understand that in some embodiments, the number of rows in theplurality of rows for placing first cells 202 is different from thenumber of rows in the plurality of rows for placing second cells 204(not shown).

In some embodiments, cells 202 and 204 are standard cells. The standardcells include, but are not limited to, an INV, AND, OR, NAND, NOR, XOR,AOI, OAI, MUX, BUFF, adder, filler, flip-flop, latch, delay, clock cell,or the like. Alternatively, cells 202 and 204 are custom cells. Cells202 and 204 are placed, during a placement stage, by an APR tool.

Each of first cells 202 has a substantially rectangular shape whichincludes a top boundary 212A, a bottom boundary 212B, and opposite sideboundaries 212C. Top boundary 212A and bottom boundary 212B are parallelto the X direction. Side boundaries 212C are parallel to the Ydirection. The height of each first cell 202, i.e., the cell height CH1,is defined between top boundary 212A and bottom boundary 212B. Likewise,each of second cells 204 has a substantially rectangular shape whichincludes a top boundary 214A, a bottom boundary 214B, and opposite sideboundaries 214C. Top boundary 214A and bottom boundary 214B are parallelto the X direction. Side boundaries 214C are parallel to the Ydirection. The height of each second cell 204, i.e., the cell heightCH2, is defined between top boundary 214A and bottom boundary 214B. Asfirst cells 202 in one row, e.g., Row 1 or Row 3, abut second cells 204in an adjacent row, e.g., Row or Row 4, top and bottom boundaries 214A,214B of second cells 204 are merged with corresponding top and bottomboundaries 212A, 212B of first cells 202 in adjacent rows, Row 1-Row 4.For example, in FIG. 2A, top boundaries 214A of second cells 204 in Row2 are merged with bottom boundaries 212B of first cells 202 in Row 1,bottom boundaries 214B of second cells 204 in Row 2 are merged with topboundaries 212A of first cells 202 in Row 3, and top boundaries 214A ofsecond cells 204 in Row 4 are merged with bottom boundaries of firstcells 202 in Row 3.

Layout diagram 200A further includes a plurality of power rails, e.g.,206 a-206 e, extending along boundaries of the plurality of rows Row1-Row 4. In FIG. 2A, power rail 206 b is present at the common boundaryof Row 1 and Row 2, power rail 206 c is present at the common boundaryof Row 2 and Row 3, and power rail 206 d is present at the commonboundary of Row 3 and Row 4. Each of power rails 206 a-206 e is used toprovide one of a source voltage potential Vdd and a ground voltagepotential Vss to a cell 202 or 204 in a corresponding row 1-Row 4. Powerrails 206 a-206 e are rectangular with long axes substantially alignedwith corresponding horizontal routing tracks, e.g., HT1, HT7, HT11, HT17and HT21. In some embodiments, top boundary 212A of each first cell 202is defined in the middle of a corresponding power rail 206 a or 206 c,and bottom boundary 212B of each first cell 202 is defined in the middleof a corresponding power rail 206 b or 206 b. Also, top boundary 214A ofeach second cell 204 is defined in the middle of a corresponding powerrail 206 b or 206 d, and bottom boundary 214B of each second cell 204 isdefined in the middle of a corresponding power rail 206 c or 206 e.

Each of first cells 202 includes a plurality of first conductive lines220, 222, 224, 226 and 228 within top and bottom boundaries 212A, 212Bthereof. First conductive lines 220, 222, 224, 226 and 228 in each offirst cells 202 are arranged substantially parallel to one another alongthe X direction and aligned with corresponding horizontal routingtracks, e.g., HT2-HT6 and HT12-HT16. Each of second cells 204 includes aplurality of second conductive lines 232, 234 and 236 within top andbottom boundaries 214A, 214B thereof. Second conductive lines 232, 234and 236 in each of second cells 204 are arranged substantially parallelto one another along the X direction and aligned with correspondinghorizontal routing tracks, e.g., HT8-HT10 and HT18-20.

In some embodiments, power rails 206 a-206 e and conductive lines220-228 and 232-236 are formed within a first metal layer, i.e., M1layer that is close to a substrate where active components of cells 202and 204, e.g., transistors or the like, are formed. During a routingstage, power rails 206 a-e and conductive lines 220-228 and 232-236 arelaid out with respect to the corresponding horizontal routing tracksHT1-HT21 by the APR tool.

Referring to FIG. 1 and FIG. 2B, method 100 proceeds to operation 104 inwhich a plurality of first cell pins 240 for each first cell 202 isplaced along corresponding vertical routing tracks of the plurality ofvertical routing tracks VT1-VT20. FIG. 2B is a layout diagram 200B oflayout diagram 200A after placing a plurality of first cell pins 240along corresponding vertical routing tracks of the plurality of verticalrouting tracks VT1-VT20 for each first cell 202, in accordance with someembodiments.

A cell pin described herein refers to a conductive line that carries aninput or output signal for a cell. In some embodiments and in FIG. 2B,the plurality of first cell pins 240 within each first cell 202comprises at least one input pin adapted to receive an input signal intothe cell or at least one output pin adapted to transfer an output signalfrom the cell. The numbers of input pins and output pins within eachfirst cell 202 are adjusted according to actual circuit demands. Forexample, the leftmost first cell 202 in Row 1 includes three first cellpins 240(1)-240(3) in which first cell pins 240(1) and 240(2) are usedas input pins and first cell pin 240(3) is used as an output pin; whilethe leftmost first cell 202 in Row 3 includes two first cell pins240(4)-240(5) in which first cell pin 240(4) is used as an input pin andfirst cell pin 240(5) is used as an output pin.

Each first cell pin 240 extends in the Y-direction and is aligned with acorresponding vertical routing track of the plurality of verticalrouting tracks VT1-VT20. Each first cell pin 240 is rectangular and hasa length along the Y-direction and a width along the X direction. Thelength of first cell pins 240 is equal to or greater than a minimumlength that is specified by a first design rule for a particularmanufacturing process, and thus satisfies the design rule line lengthrequirement. As used herein, the minimum length of a manufacturingprocess is the smallest length in which a conductive line can befabricated while still satisfying the corresponding design rule so as toavoid erroneous circuit function. In some embodiments, a second designrule imposes a minimum boundary offset between ends of first cell pin240 and top and bottom boundaries 212A, 212B of first cell 202. Firstcell pins 240 thus reside within top and bottom boundaries 212A, 212Bsuch that no first cell pin 240 terminates at a top or bottom edge 212Aor 212B of first cells 202 to satisfy the minimum boundary offsetguidelines. In some embodiments, first cell pins 240 extend across theentire set of first conductive lines 220-228 enclosed in first cells202.

Each first cell pin 240 is assigned with a color the same as the colorof the corresponding vertical routing track VT1-VT20 along which thefirst cell pin 240 extends. In some embodiments, a first set of firstcell pins 240 extending along odd numbered vertical routing tracks VT1,VT3 . . . VT19 are assigned the first color, e.g., color A, and a secondset of first cell pins 240 extending along even numbered verticalrouting tracks VT2, VT4 . . . VT20 are assigned the second color, e.g.,color B, indicating that the first set of first cell pins 240 are formedusing a first mask and the second set of first cell pins 240 are formedusing a second mask different from the first mask.

In some embodiments, first cell pins 240 are located within a secondmetal layer, i.e., M2 layer, overlying the M1 layer. First cell pins 240are electrically coupled to corresponding first conductive lines 220-228by way of a plurality of first vias 242 arranged below first cell pins240. Each first via 242 is at an intersection between a first cell pin240 and a corresponding first conductive line 220-228.

Referring to FIG. 1 and FIG. 2C, method 100 proceeds to operation 106 inwhich a plurality of via placement points 250 are identified for each ofsecond cells 204. FIG. 2C is a layout diagram 200C of layout diagram200B after identifying the plurality of via placement points 250 foreach of second cells 204, in accordance with some embodiments.

Via placement points 250 correspond to possible locations for placingvias 262 (FIG. 2E) that electrically connect second conductive lines232-236 in the M1 layer to second cell pins 260 (FIG. 2D) to be formedin the overlying M2 layer, thereby enabling device signal transmission.Via placement points 250 are located at intersections of secondconductive lines 232-236 and corresponding vertical routing tracks invertical routing tracks VT1-VH20. For example, for the leftmost secondcell 204 in Row 2, two exemplary via placement points 250(1) and 250(2)are identified as possible locations for placing vias over a secondconductive line 232 laid on horizontal routing track HT8, two exemplaryvia placement points 250(3) and 250(4) are identified as possiblelocations for placing vias over a second conductive line 234 laid onhorizontal routing track HT9, and two exemplary via placement points250(5) and 250(6) are identified as possible locations for placing viasover a second conductive line 236 laid on horizontal routing track HT9.

Referring to FIG. 1 and FIG. 2D, method 100 proceeds to operation 108 inwhich a plurality of second cell pins 260 for each second cell 204 isplaced over a plurality of selected via placement points 250. FIG. 2D isa layout diagram 200D of layout diagram 200C after placing a pluralityof second cell pins 260 over a plurality of selected via placementpoints 250 for each second cell 204, in accordance with someembodiments.

In some embodiments, a third design rule imposes a minimum end-to-endspacing requirement that specifies that facing ends of adjacent cellpins on the same vertical routing track must be a minimum distanceapart. The minimum end-to-end spacing is a parameter of a particularprocess technology node. In operation 108, via placement points 250identified in operation 106 are checked to determine whether there is asufficient space available to place a second cell pin 260 over a viaplacement point 250 such that the second cell pin 260 is separated froman adjacent first cell pin 240 that is on the same vertical routingtrack VT1-VT20 as the second cell pin 260 by the minimum end-to-endspacing. After checking, a subset of via placement points 250 suitablefor placing second cell pins 260 for second cells 204 are selectedCriteria for selecting via placement points 250 for placing second cellpins 260 to satisfy the minimum end-to-end spacing requirement areillustrated and described below using exemplary second cell pins260(1)-260(3) and exemplary via placement points 250(1)-250(6)identified for the leftmost second cell 204 in Row 2. A second cell pin260(1) can be placed either over via placement point 250(3) or over viaplacement point 250(6) along vertical routing track VT2 without causinga minimum end-to-end spacing violation. This is so because in rows,i.e., Row 1 and Row 3 that are immediately adjacent to Row 2, only theleftmost first cell 202 in Row 3 contains a first cell pin 240(4) alongthe same vertical routing track VT2, while a portion of vertical routingtrack VT2 in Row 1 is unoccupied. Second cell pin 260 (1) thus can beextended to cross top boundary 214A of second cell 204 and onto theunoccupied portion of vertical routing track VT2 in the leftmost firstcell 202 of Row 1 to ensure that an end of second cell pin 260(1) isspaced from an adjacent end of first cell pin 240(4) by a distance thatis equal to or greater than the minimum end-to-end spacing. Similarly,along vertical routing track VT5, a second cell pin 260(2) can be placedover via placement point 250(2) without causing a minimum end-to-endspacing violation. This is so because none of the leftmost first cells202 in Row 1 and Row 3 contains a first cell pin 240 along the samevertical routing track VT5 to trigger the minimum end-to-end spacingviolation so as to prevent placement of the second cell pin 260(2) overvia placement point 250(2). In some embodiments, second cell pin 260(2)can be formed to have both ends terminated at opposite top and bottomboundaries 214A and 214B of the leftmost second cell 204 in Row 2. Inother embodiments, second cell pin 2602(2) can be formed to have an endterminated within the leftmost second cell 204 in Row 2 and an oppositeend extending across a corresponding boundary 214A or 214B and onto aportion of vertical routing track VT5 in Row 1 or onto a portion ofvertical routing track VT5 in Row 3 because both portions of verticalrouting track VT5 in Row 1 and Row 3 are unoccupied. In contrast,placing a cell pin 260′ over via placement point 250(1) along verticalrouting track VT4 is forbidden by the minimum end-to-end spacingrequirement as indicated by the cross symbol because each of theleftmost first cells 202 in Row 1 and Row 3 contains a first cell pin240(2) or 240(5) along the same vertical routing track VT4 and nosufficient space is available to accommodate a cell pin therebetweenwithout causing a minimum end-to-end spacing violation. Placing cell pin260′ between two first cell pins 240(2) and 240(5) in Row 1 and Row 3along the same vertical routing track VT4 would trigger a minimumend-to-end spacing violation as the distance D1 between facing ends ofcell pin 260′ and first cell pin 240(2) in Row 1 or the distance D2between facing ends of cell pin 260′ and first cell pin 240(5) in Row 3is less than the minimum end-to-end spacing. If cell pin 260′ is placedover via placement point 250(1) along vertical routing track VT4,manufacturing an IC from layout diagram 200F (FIG. 2F) has an increasedrisk of resulting in a faulty circuit.

Subsequently, second cell pins 260 configured to input and outputsignals to second cells 204 are placed over the selected via placementpoints 250 extending along corresponding vertical routing tracksVT1-VT21 where the selected via placement points 250 are located.Accordingly, in compliance with the minimum end-to-end spacingrequirement, in some embodiments, a second cell pin 260 for a secondcell 204 can be formed to have one end terminated within a correspondingtop or bottom boundary 214A or 214B and an opposite end extending acrossa corresponding top or bottom boundary 214A or 214B into an adjacentfirst cell 202 that does not contain a first cell pin 240 on the samevertical routing track VT1-VT20. In this case, the second cell pin 260can be formed of any length such that in some embodiments, second cellpin 260 has a length equal to or greater than the minimum line length.In this case, second cell pin 260 has a length less than the minimumline length. In instances where adjacent vertical tracks VT1-VT20 areassigned with different colors, second cell pins 260 on adjacentvertical routing tracks VT1-VT20 are also assigned with differentcolors, Color A or Color B, indicating that adjacent second cell pins260 are fabricated by different masks.

Referring to FIG. 1 and FIG. 2E, method 100 proceeds to operation 110 inwhich a plurality of second vias 262 is placed to couple the pluralityof second cell pins 260 to the plurality of second conductive lines232-236. FIG. 2E is a layout diagram 200E of layout diagram 200D afterplacing a plurality of second vias 262 to couple the plurality of secondcell pins 260 to the plurality of second conductive lines 232-236, inaccordance with some embodiments.

Second cell pins 260 are electrically coupled to correspondingunderlying second conductive lines 232-236 through second vias 262.Second vias 262 are placed at locations of those via placement points250 selected in operation 108.

Referring to FIG. 1 and FIG. 2F, method 100 proceeds to operation 112 inwhich at least one second cell pin 260 and/or at least one first cellpin 240 are elongated. FIG. 2F is a layout diagram 200F of layoutdiagram 200F after elongating first and second cell pins 240 and 260, inaccordance with some embodiments.

In operation 112, at least one second cell pin 260 among second cellpins 260 is elongated along the Y-direction so that all second cell pins260 have a length equal to or greater than the minimum line length. Theelongation of second cell pins 260 helps to improve pin accessibility,thereby helping to provide better routing efficiency and routing densityfor second cells 204. Likewise, in some embodiments, at least one firstcell pin 240 among first cell pins 240 is elongated along theY-direction crossing a corresponding boundary 212A or 212B of a firstcell 202 where the at least one first cell pin 240 is located. Theelongation of first cell pins 240 helps to improve pin accessibility,thereby helping to provide better routing efficiency and routing densityfor first cells 202. Each of first and second cell pins 240 and 260 canbe elongated to any length as long as the minimum end-to-end spacingrequirement is satisfied between facing ends of adjacent first cell pin240 and second cell pin 260 on the same vertical routing track VT1-VT30after pin elongation.

FIG. 3 is a flowchart of a method 300 of generating layout diagram 200F,in accordance with some embodiments. In various embodiments, theoperations of method 300 are performed in the order depicted in FIG. 3or in one or more orders other than the order depicted in FIG. 3 . Insome embodiments, one or more additional operations are performedbefore, between, during, and/or after one or more operations of method300. Method 300 is describe below in conjunction with FIGS. 4A-4C wherevarious stages of generating layout diagram 200F are illustrated. Unlessspecified otherwise, components in FIGS. 4A-4C that are essentially thesame as their like components in FIGS. 2A-2F, are denoted by likereference numerals shown in FIGS. 2A-2F.

Similar to method 100, some or all of the operations of method 300 arecapable of being performed as part of the APR tool. In some embodiments,some or all of method 300 is executed by a processor of a computer. Insome embodiments, some or all of method 300 is executed by a processor502 of an EDA system 500, discussed below with respect to FIG. 5 . Insome embodiments, some or all of the operations of method 300 arecapable of being performed as part of a design procedure performed in adesign house, e.g., a design house 620 discussed below with respect toFIG. 6 .

Referring to FIG. 3 , method 300 includes operation 302 in which aplurality of first conductive lines 220-228 for a plurality of firstcells 202 of a first cell height and a plurality of second conductivelines for 232-236 for a plurality of second cell 204 of a second cellheight CH1 less than the first cell height CH2 are placed alongcorresponding horizontal routing tracks HT1-HT21 of a routing grid;first and second cells 202 and 204 are arranged into a plurality ofrows. Operation 302 is essentially the same as operation 102, and layoutdiagram 200A is generated after operation 302.

Referring to FIG. 3 and FIG. 4A, method 300 proceeds to operation 304 inwhich a plurality of first via placement points 270 are identified foreach of first cells 202 and a plurality of second via placement points250 are identified for each of second cells 204. FIG. 4A is a layoutdiagram 400A of layout diagram 200A after identifying a plurality offirst via placement points 270 for each of first cells 202 and aplurality of second via placement points 250 for each of second cells204, in accordance with some embodiments.

First via placement points 270 correspond to possible locations forplacing first vias 242 (FIG. 4C) configured to electrically connectfirst conductive lines 220-228 in the M1 layer to first cell pins 240(FIG. 4B) to be formed in the overlying M2 layer, thereby enablingsignal transmission for first cells 202. First via placement points 270are located at intersections of first conductive lines 220-2228 andcorresponding vertical routing tracks in vertical routing tracksVT1-VT20.

Likewise, second via placement points 250 correspond to possiblelocations for placing second vias 262 (FIG. 4C) configured toelectrically connect second conductive lines 232-236 in the M1 layer tosecond cell pins 260 (FIG. 4B) to be formed in the overlying M2 layer,thereby enabling signal transmission for second cells 204. Second viaplacement points 250 are located at intersections of second conductivelines 232-236 and corresponding vertical routing tracks in verticalrouting tracks VT1-VT20.

Referring to FIG. 3 and FIG. 4B, method 300 proceeds to operation 306 inwhich a plurality of first cell pins 240 is placed over the selectedfirst via placement points 270 along corresponding vertical routingtracks VT1-VT20 and a plurality of second cell pins 260 is placed overthe selected second via placement points 250 along correspondingvertical routing tracks VT1-VT20. FIG. 4B is a layout diagram 400B oflayout diagram 400A after placing a plurality of first cell pins 240over the selected first via placement points 270 along correspondingvertical routing tracks VT1-VT20 and a plurality of second cell pins 260over the selected second via placement points 250 along correspondingvertical routing tracks VT1-VT20.

An algorithm is iteratively performed on all of via placement points 270and 250 to evaluate free spaces available around first via placementpoints 270 and second via placement points 250. Based on the availablefree spaces, some first via placement points 270 and second viaplacement points 250 are selected such that placement of first cell pins240 and second cell pins 270 on the corresponding selected via placementpoints 270 and 250 does not cause any violation of the minimumend-to-end spacing requirement as a first cell pin 240 and a second cellpin 260 for adjacent first and second cells 202 and 204 are placed onthe same vertical routing track VT1-VT20.

Those first via placement points 270 suitable for placing first cellpins 240 and those second via placement points 250 suitable for placingsecond cell pins 260 are selected based on different design constraintsapplied to first cells pins 240 and second cell pins 260. For example,because first cells 202 have a relatively large cell height CH1 whichallows first cells 202 to accommodate cell pins with a length equal toor greater than a minimum length, first cell pins 240 are able to beformed to conform to both of the minimum length requirement and theminimum boundary offset requirement. Accordingly, each first cell pin240 is formed to have both ends terminated within top and bottomboundaries 212A and 212B of first cells 202. On the contrary, becausesecond cells 204 have a relatively small cell height CH2 which onlyallows second cells 204 to accommodate cell pins with a length less thanthe minimum length, second cell pins 260 are not able to be formed toconform to the minimum length requirement and the minimum boundaryoffset requirement. Accordingly, each second cell pin 260 is eitherconfigured to have both ends terminated at top and bottom boundaries214A and 214B of a second cell 204 when no first cell pins 240 arepresent on the same vertical routing tracking VT1-VT20 in adjacent rows,Row 1 and Row 3, or configured to have one end terminated within top andbottom boundaries 214A and 214B and another end extending across acorresponding top or boundary 214A or 214B of a second cell 204 into anadjacent row, Row 1 or Row 3, when only one first cell pin 240 ispresent on the same vertical routing track VT1-VT20 in Row 1 or Row 3.By applying different design constraints to first cell pins 240 andsecond cell pins 260, first cell pins 240 and second cell pins 260 canbe placed such that facing ends of two adjacent first cell pins 240 andsecond cell pin 260 on the same vertical routing track VT1-VT20 satisfythe minimum end-to-end spacing requirement.

Subsequently, first cell pins 240 configured to input and output signalsto first cells 202 are placed over the selected first via placementpoints 270 to extend along corresponding vertical routing tracksVT1-VT21 where the selected first via placement points 270 are located.And second cell pins 260 configured to input and output signals tosecond cells 204 are placed over the selected second via placementpoints 250 to extend along corresponding vertical routing tracksVT1-VT21 where the selected second via placement points 250 are located.

Referring to FIG. 3 and FIG. 4C, method 300 proceeds to operation 308 inwhich a plurality of first vias 242 is placed to couple the plurality offirst cell pins 240 to the plurality of first conductive lines 220-228and a plurality of second vias 262 is placed to couple the plurality ofsecond cell pins 260 to the plurality of second conductive lines232-236. FIG. 4C is a layout diagram 400C of layout diagram 400B afterplacing a plurality of first vias 242 to couple the plurality of firstcell pins 240 to the plurality of first conductive lines and placing aplurality of second vias 262 to couple the plurality of second cell pins260 to the plurality of second conductive lines 232-236, in accordancewith some embodiments.

First cell pins 240 are electrically coupled to corresponding underlyingfirst conductive lines 220-228 through first vias 242. First vias 242are placed at locations of those via placement points 270 selected inoperation 306. Likewise, second cell pins 260 are electrically coupledto corresponding underlying second conductive lines 232-236 throughsecond vias 262. Second vias 262 are placed at locations of those viaplacement points 250 selected in operation 308.

Referring to FIG. 3 and FIG. 2F, method 300 proceeds to operation 310 inwhich at least one second cell pin 260 and/or at least one first cellpin 240 are elongated. Operation 310 is essentially the same asoperation 112, and layout diagram 200F is generated after operation 310.

In the present disclosure, by using different design constraints inplacing cell pins for cells of different cell heights, the routing forcells of different heights in a hybrid cell design is able to beperformed under the same design block without pushing existing designrules. As a result, a 10% increase in pin placement utilization isachieved.

FIG. 5 is a block diagram of an electronic design automation (EDA)system 500 in accordance with some embodiments.

In some embodiments, EDA system 500 includes an APR tool. Methodsdescribed herein of designing layout diagrams represent wire routingarrangements, in accordance with one or more embodiments, areimplementable, for example, using EDA system 500, in accordance withsome embodiments.

In some embodiments, EDA system 500 is a general purpose computingdevice including a hardware processor 502 and a non-transitory,computer-readable storage medium 504. Storage medium 504, amongst otherthings, is encoded with, i.e., stores, computer program code 506, wherecomputer program code 506 is a set of computer-executable instructions.Execution of computer program code 506 by processor 502 represents (atleast in part) an APR tool which implements a portion or all of, e.g.,the methods described herein in accordance with one or more(hereinafter, the noted processes and/or methods).

Processor 502 is electrically coupled to computer-readable storagemedium 504 via a bus 508. Processor 502 is also electrically coupled toan I/O interface 510 by bus 508. A network interface 512 is alsoelectrically connected to processor 502 via bus 508. Network interface512 is connected to a network 514, so that processor 502 andcomputer-readable storage medium 504 are capable of connecting toexternal elements via network 514. Processor 502 is configured toexecute computer program code 506 encoded in computer-readable storagemedium 504 in order to cause EDA system 500 to be usable for performinga portion or all of the noted processes and/or methods. In one or moreembodiments, processor 502 is a central processing unit (CPU), amulti-processor, a distributed processing system, an applicationspecific integrated circuit (ASIC), and/or a suitable processing unit.

In one or more embodiments, computer-readable storage medium 504 is anelectronic, magnetic, optical, electromagnetic, infrared, and/or asemiconductor system (or apparatus or device). For example,computer-readable storage medium 504 includes a semiconductor orsolid-state memory, a magnetic tape, a removable computer diskette, arandom access memory (RAM), a read-only memory (ROM), a rigid magneticdisk, and/or an optical disk. In one or more embodiments using opticaldisks, computer-readable storage medium 504 includes a compact disk-readonly memory (CD-ROM), a compact disk-read/write (CD-R/W), and/or adigital video disc (DVD).

In one or more embodiments, storage medium 504 stores computer programcode 506 configured to cause EDA system 500 (where such executionrepresents (at least in part) the APR tool) to be usable for performinga portion or all of the noted processes and/or methods. In one or moreembodiments, storage medium 504 also stores information whichfacilitates performing a portion or all of the noted processes and/ormethods. In one or more embodiments, storage medium 504 stores library507 of standard cells including such standard cells corresponding tocells disclosed herein.

EDA system 500 includes I/O interface 510. I/O interface 510 is coupledto external circuitry. In one or more embodiments, I/O interface 510includes a keyboard, keypad, mouse, trackball, trackpad, touchscreen,and/or cursor direction keys for communicating information and commandsto processor 502.

EDA system 500 also includes network interface 512 coupled to processor502. Network interface 512 allows EDA system 500 to communicate withnetwork 514, to which one or more other computer systems are connected.Network interface 512 includes wireless network interfaces such asBLUETOOTH, WIFI, WIMAX, GPRS, or WCDMA; or wired network interfaces suchas ETHERNET, USB, or IEEE-1364. In one or more embodiments, a portion orall of noted processes and/or methods, is implemented in two or moresystems 500.

EDA system 500 is configured to receive information through I/Ointerface 510. The information received through I/O interface 510includes one or more of instructions, data, design rules, libraries ofstandard cells, and/or other parameters for processing by processor 502.The information is transferred to processor 502 via bus 508. EDA system500 is configured to receive information related to a UI through I/Ointerface 510. The information is stored in computer-readable medium 504as user interface (UI) 542.

In some embodiments, a portion or all of the noted processes and/ormethods is implemented as a standalone software application forexecution by a processor. In some embodiments, a portion or all of thenoted processes and/or methods is implemented as a software applicationthat is a part of an additional software application. In someembodiments, a portion or all of the noted processes and/or methods isimplemented as a plug-in to a software application. In some embodiments,at least one of the noted processes and/or methods is implemented as asoftware application that is a portion of an APR tool. In someembodiments, a portion or all of the noted processes and/or methods isimplemented as a software application that is used by EDA system 500. Insome embodiments, a layout diagram which includes standard cells isgenerated using a tool such as VIRTUOSO® available from CADENCE DESIGNSYSTEMS, Inc., or another suitable layout generating tool.

In some embodiments, the processes are realized as functions of aprogram stored in a non-transitory computer readable recording medium.Examples of a non-transitory computer readable recording medium include,but are not limited to, external/removable and/or internal/built-instorage or memory unit, e.g., one or more of an optical disk, such as aDVD, a magnetic disk, such as a hard disk, a semiconductor memory, suchas a ROM, a RAM, a memory card, and the like.

FIG. 6 is a block diagram of an IC manufacturing system 600, and an ICmanufacturing flow associated therewith, in accordance with someembodiments.

In some embodiments, based on a layout diagram, at least one of (A) oneor more semiconductor masks or (B) at least one component in a layer ofa semiconductor integrated circuit is fabricated using IC manufacturingsystem 600.

In FIG. 6 , IC manufacturing system 600 includes entities, such as adesign house 620, a mask house 630, and an IC manufacturer/fabricator(“fab”) 650, that interact with one another in the design, development,and manufacturing cycles and/or services related to manufacturing an ICdevice 660. The entities in system 600 are connected by a communicationsnetwork. In some embodiments, the communications network is a singlenetwork. In some embodiments, the communications network is a variety ofdifferent networks, such as an intranet and the Internet. Thecommunications network includes wired and/or wireless communicationchannels. Each entity interacts with one or more of the other entitiesand provides services to and/or receives services from one or more ofthe other entities. In some embodiments, two or more of design house620, mask house 630, and IC fab 650 is owned by a single larger company.In some embodiments, two or more of design house 820, mask house 630,and IC fab 650 coexist in a common facility and use common resources.

Design house (or design team) 620 generates an IC design layout diagram622. IC design layout diagram 622 includes various geometrical patternsdesigned for an IC device 660. The geometrical patterns correspond topatterns of metal, oxide, or semiconductor layers that make up thevarious components of IC device 660 to be fabricated. The various layerscombine to form various IC features. For example, a portion of IC designlayout diagram 622 includes various IC features, such as an activeregion, gate electrode, source and drain, conductive lines or vias of aninterlayer interconnection, and openings for bonding pads, to be formedin a semiconductor substrate (such as a silicon wafer) and variousmaterial layers disposed on the semiconductor substrate. Design house620 implements a proper design procedure to form IC design layoutdiagram 622. The design procedure includes one or more of logic design,physical design or place and route. IC design layout diagram 622 ispresented in one or more data files having information of thegeometrical patterns. For example, IC design layout diagram 622 can beexpressed in a GDSII file format or DFII file format.

Mask house 630 includes data preparation 632 and mask fabrication 644.Mask house 630 uses IC design layout diagram 622 to manufacture one ormore masks 645 to be used for fabricating the various layers of ICdevice 660 according to IC design layout diagram 622. Mask house 630performs mask data preparation 632, where IC design layout diagram 622is translated into a representative data file (“RDF”). Mask datapreparation 632 provides the RDF to mask fabrication 644. Maskfabrication 644 includes a mask writer. A mask writer converts the RDFto an image on a substrate, such as a mask (reticle) 645 or asemiconductor wafer 653. The design layout diagram 622 is manipulated bymask data preparation 632 to comply with particular characteristics ofthe mask writer and/or requirements of IC fab 650. In FIG. 6 , mask datapreparation 632 and mask fabrication 644 are illustrated as separateelements. In some embodiments, mask data preparation 632 and maskfabrication 644 can be collectively referred to as mask datapreparation.

In some embodiments, mask data preparation 632 includes opticalproximity correction (OPC) which uses lithography enhancement techniquesto compensate for image errors, such as those that can arise fromdiffraction, interference, other process effects and the like. OPCadjusts IC design layout diagram 862. In some embodiments, mask datapreparation 632 includes further resolution enhancement techniques(RET), such as off-axis illumination, sub-resolution assist features,phase-shifting masks, other suitable techniques, and the like orcombinations thereof. In some embodiments, inverse lithographytechnology (ILT) is also used, which treats OPC as an inverse imagingproblem.

In some embodiments, mask data preparation 632 includes a mask rulechecker (MRC) that checks the IC design layout diagram 622 that hasundergone processes in OPC with a set of mask creation rules whichcontain certain geometric and/or connectivity restrictions to ensuresufficient margins, to account for variability in semiconductormanufacturing processes, and the like. In some embodiments, the MRCmodifies the IC design layout diagram 622 to compensate for limitationsduring mask fabrication 644, which may undo part of the modificationsperformed by OPC in order to meet mask creation rules.

In some embodiments, mask data preparation 632 includes lithographyprocess checking (LPC) that simulates processing that will beimplemented by IC fab 650 to fabricate IC device 660. LPC simulates thisprocessing based on IC design layout diagram 622 to create a simulatedmanufactured device, such as IC device 660. The processing parameters inLPC simulation can include parameters associated with various processesof the IC manufacturing cycle, parameters associated with tools used formanufacturing the IC, and/or other aspects of the manufacturing process.LPC takes into account various factors, such as aerial image contrast,depth of focus (“DOF”), mask error enhancement factor (“MEEF”), othersuitable factors, and the like or combinations thereof. In someembodiments, after a simulated manufactured device has been created byLPC, if the simulated device is not close enough in shape to satisfydesign rules, OPC and/or MRC are be repeated to further refine IC designlayout diagram 622.

It should be understood that the above description of mask datapreparation 632 has been simplified for the purposes of clarity. In someembodiments, data preparation 632 includes additional features such as alogic operation (LOP) to modify the IC design layout diagram 622according to manufacturing rules. Additionally, the processes applied toIC design layout diagram 622 during data preparation 632 may be executedin a variety of different orders.

After mask data preparation 632 and during mask fabrication 644, a mask645 or a group of masks 645 are fabricated based on the modified ICdesign layout diagram 622. In some embodiments, mask fabrication 644includes performing one or more lithographic exposures based on ICdesign layout diagram 822. In some embodiments, an electron-beam(e-beam) or a mechanism of multiple e-beams is used to form a pattern ona mask (photomask or reticle) 645 based on the modified IC design layoutdiagram 622. Mask 645 can be formed in various technologies. In someembodiments, mask 645 is formed using binary technology. In someembodiments, a mask pattern includes opaque regions and transparentregions. A radiation beam, such as an ultraviolet (UV) beam, used toexpose the image sensitive material layer (e.g., photoresist) which hasbeen coated on a wafer, is blocked by the opaque region and transmitsthrough the transparent regions. In one example, a binary mask versionof mask 645 includes a transparent substrate (e.g., fused quartz) and anopaque material (e.g., chromium) coated in the opaque regions of thebinary mask. In another example, mask 645 is formed using a phase shifttechnology. In a phase shift mask (PSM) version of mask 645, variousfeatures in the pattern formed on the phase shift mask are configured tohave proper phase difference to enhance the resolution and imagingquality. In various examples, the phase shift mask can be attenuated PSMor alternating PSM. The mask(s) generated by mask fabrication 644 isused in a variety of processes. For example, such a mask(s) is used inan ion implantation process to form various doped regions insemiconductor wafer 653, in an etching process to form various etchingregions in semiconductor wafer 653, and/or in other suitable processes.

IC fab 650 includes wafer fabrication 652. IC fab 650 is an ICfabrication business that includes one or more manufacturing facilitiesfor the fabrication of a variety of different IC products. In someembodiments, IC Fab 650 is a semiconductor foundry. For example, theremay be a manufacturing facility for the front end fabrication of aplurality of IC products (front-end-of-line (FEOL) fabrication), while asecond manufacturing facility may provide the back end fabrication forthe interconnection and packaging of the IC products (back-end-of-line(BEOL) fabrication), and a third manufacturing facility may provideother services for the foundry business.

IC fab 650 uses mask(s) 645 fabricated by mask house 630 to fabricate ICdevice 660. Thus, IC fab 650 at least indirectly uses IC design layoutdiagram 622 to fabricate IC device 660. In some embodiments,semiconductor wafer 653 is fabricated by IC fab 650 using mask(s) 645 toform IC device 660. In some embodiments, the IC fabrication includesperforming one or more lithographic exposures based at least indirectlyon IC design layout diagram 622. Semiconductor wafer 653 includes asilicon substrate or other proper substrate having material layersformed thereon. Semiconductor wafer 653 further includes one or more ofvarious doped regions, dielectric features, multilevel interconnects,and the like (formed at subsequent manufacturing steps).

Details regarding an integrated circuit (IC) manufacturing system (e.g.,system 600 of FIG. 6 ), and an IC manufacturing flow associatedtherewith are found, e.g., in U.S. Pat. No. 9,256,709, granted Feb. 9,2016, U.S. Pre-Grant Publication No. 20150278429, published Oct. 1,2015, U.S. Pre-Grant Publication No. 20140040838, published Feb. 6,2014, and U.S. Pat. No. 7,260,442, granted Aug. 21, 2007, the entiretiesof each of which are hereby incorporated by reference.

An aspect of this description relates to a method of generating a layoutdiagram for an integrated circuit. The method includes arranging aplurality of cells in the layout diagram, wherein each cell of theplurality of cells comprises a first power rail along a first boundaryand a second power rail along a second boundary, and the first boundaryis spaced from the second boundary in a first direction. The methodfurther includes placing a plurality of cell pins over a plurality ofselected via placement points in a first cell of the plurality of cellsin accordance with a design rule, wherein a first cell pin of theplurality of cell pins has a first end spaced from both the first powerrail and the second power rail in the first direction. In someembodiments, placing the plurality of cell pins includes placing asecond cell pin of the plurality of cell pins having a second endaligned with an edge of the first power rail outside the first cell. Insome embodiments, placing the plurality of cell pins includes placingthe first cell pin extending beyond the first power rail in the firstdirection. In some embodiments, placing the plurality of cell pinsincludes placing the plurality of cell pin on a metal layer farther froma substrate than the first power rail. In some embodiments, the methodfurther includes retrieving the plurality of cells from a cell library.In some embodiments, placing the plurality of cell pins includes placingthe first cell pin extending only in the first direction. In someembodiments, placing the plurality of cell pins includes placing theplurality of cell pins using an automatic placement routing (APR) tool.In some embodiments, the method further includes fabricating at leastone mask based on the layout diagram for forming the integrated circuit.

An aspect of this description relates to a method of generating a layoutdiagram for an integrated circuit. The method includes arranging aplurality of cells in the layout diagram, wherein each cell of theplurality of cells comprises a first power rail along a first boundaryand a second power rail along a second boundary, and the first boundaryis spaced from the second boundary in a first direction. The methodfurther includes placing a plurality of cell pins over a plurality ofselected via placement points in a first cell of the plurality of cellsin accordance with a design rule, wherein a first cell pin of theplurality of cell pins overlaps the first power rail between theadjacent cells of the plurality of cells. In some embodiments, themethod further includes placing a via at a first via placement point ofthe plurality of selected via placement points, wherein the via overlapsthe first cell pin. In some embodiments, placing the plurality of cellpins includes placing a second cell pin of the plurality of cell pinsentirely within a first cell of the plurality of cells. In someembodiments, placing the second cell pin includes placing the secondcell pin overlapping with a first via placement point of the pluralityof selected via placement points. In some embodiments, arranging theplurality of cells includes abutting the adjacent cells in the firstdirection. In some embodiments, placing the plurality of cell pinsincludes placing the plurality of cell pins satisfying a minimumend-to-end spacing requirement. In some embodiments, the method furtherincludes identifying a location of each of a plurality of via placementpoints, comprising the plurality of selected via placement points, basedon an intersection of conductive lines at different levels of theintegrated circuit. In some embodiments, the method further includesselecting each of the plurality of selected via placement points fromthe plurality of via placement points based on a spacing requirement. Insome embodiments, the method further includes instructing at least onemanufacturing tool to manufacture the integrated circuit including thefirst pin cell.

An aspect of this description relates to a system for generating anintegrated circuit. The system includes a non-transitory computerreadable medium configured to store instructions thereon. The systemfurther includes a processor connected to the non-transitory computerreadable medium. The processor is configured to execute the instructionsfor arranging a plurality of cells in the layout diagram, wherein eachcell of the plurality of cells comprises a first power rail along afirst boundary and a second power rail along a second boundary, and thefirst boundary is spaced from the second boundary in a first direction.The processor is further configured to execute the instructions forplacing a plurality of cell pins over a plurality of selected viaplacement points in a first cell of the plurality of cells in accordancewith a design rule, wherein a first cell pin of the plurality of cellpins has a first end spaced from both the first power rail and thesecond power rail in the first direction. In some embodiments, theprocessor is further configured to execute the instructions forarranging the plurality of cells by abutting the adjacent cells in thefirst direction. In some embodiments, the processor is furtherconfigured to execute the instructions for instructing at least onemanufacturing tool to manufacture the integrated circuit including thefirst pin cell.

The foregoing outlines features of several embodiments so that thoseskilled in the art may better understand the aspects of the presentdisclosure. Those skilled in the art should appreciate that they mayreadily use the present disclosure as a basis for designing or modifyingother processes and structures for carrying out the same purposes and/orachieving the same advantages of the embodiments introduced herein.Those skilled in the art should also realize that such equivalentconstructions do not depart from the spirit and scope of the presentdisclosure, and that they may make various changes, substitutions, andalterations herein without departing from the spirit and scope of thepresent disclosure.

What is claimed is:
 1. A method of generating a layout diagram for anintegrated circuit, the method comprising: arranging a plurality ofcells in the layout diagram, wherein each cell of the plurality of cellscomprises a first power rail along a first boundary and a second powerrail along a second boundary, and the first boundary is spaced from thesecond boundary in a first direction; and placing a plurality of cellpins over a plurality of selected via placement points in a first cellof the plurality of cells in accordance with a design rule, wherein afirst cell pin of the plurality of cell pins has a first end spaced fromboth the first power rail and the second power rail in the firstdirection.
 2. The method of claim 1, wherein placing the plurality ofcell pins comprises placing a second cell pin of the plurality of cellpins having a second end aligned with an edge of the first power railoutside the first cell.
 3. The method of claim 1, wherein placing theplurality of cell pins comprises placing the first cell pin extendingbeyond the first power rail in the first direction.
 4. The method ofclaim 1, wherein placing the plurality of cell pins comprises placingthe plurality of cell pins on a metal layer farther from a substratethan the first power rail.
 5. The method of claim 1, further comprisingretrieving the plurality of cells from a cell library.
 6. The method ofclaim 1, wherein placing the plurality of cell pins comprises placingthe first cell pin extending only in the first direction.
 7. The methodof claim 1, wherein placing the plurality of cell pins comprises placingthe plurality of cell pins using an automatic placement routing (APR)tool.
 8. The method of claim 1, further comprising fabricating at leastone mask based on the layout diagram for forming the integrated circuit.9. A method of generating a layout diagram for an integrated circuit,the method comprising: arranging a plurality of cells in the layoutdiagram, wherein each cell of the plurality of cells comprises a firstpower rail along a first boundary and a second power rail along a secondboundary, and the first boundary is spaced from the second boundary in afirst direction; and placing a plurality of cell pins over a pluralityof selected via placement points in a first cell of the plurality ofcells in accordance with a design rule, wherein a first cell pin of theplurality of cell pins overlaps the first power rail between theadjacent cells of the plurality of cells.
 10. The method of claim 9,further comprising placing a via at a first via placement point of theplurality of selected via placement points, wherein the via overlaps thefirst cell pin.
 11. The method of claim 9, wherein placing the pluralityof cell pins comprises placing a second cell pin of the plurality ofcell pins entirely within a first cell of the plurality of cells. 12.The method of claim 11, wherein placing the second cell pin comprisesplacing the second cell pin overlapping with a first via placement pointof the plurality of selected via placement points.
 13. The method ofclaim 9, wherein arranging the plurality of cells comprises abutting theadjacent cells in the first direction.
 14. The method of claim 9,wherein placing the plurality of cell pins comprises placing theplurality of cell pins satisfying a minimum end-to-end spacingrequirement.
 15. The method of claim 9, further comprising identifying alocation of each of a plurality of via placement points, comprising theplurality of selected via placement points, based on an intersection ofconductive lines at different levels of the integrated circuit.
 16. Themethod of claim 15, further comprising selecting each of the pluralityof selected via placement points from the plurality of via placementpoints based on a spacing requirement.
 17. The method of claim 9,further comprising instructing at least one manufacturing tool tomanufacture the integrated circuit including the first pin cell.
 18. Asystem for generating an integrated circuit, the system comprising: anon-transitory computer readable medium configured to store instructionsthereon; and a processor connected to the non-transitory computerreadable medium, wherein the processor is configured to execute theinstructions for: arranging a plurality of cells in the layout diagram,wherein each cell of the plurality of cells comprises a first power railalong a first boundary and a second power rail along a second boundary,and the first boundary is spaced from the second boundary in a firstdirection; and placing a plurality of cell pins over a plurality ofselected via placement points in a first cell of the plurality of cellsin accordance with a design rule, wherein a first cell pin of theplurality of cell pins has a first end spaced from both the first powerrail and the second power rail in the first direction.
 19. The system ofclaim 18, wherein the processor is further configured to execute theinstructions for arranging the plurality of cells by abutting theadjacent cells in the first direction.
 20. The system of claim 18,wherein the processor is further configured to execute the instructionsfor instructing at least one manufacturing tool to manufacture theintegrated circuit including the first pin cell.